The present invention pertains to RAM memory accesses and more particularly to shared access of memory by a processor and refresh circuitry.
Developments in the semiconductor industry during past years have resulted in a major shift of the technology for storage elements used in digital processor control systems. Semiconductor random access memory (RAM) has been developed at a very rapid pace throughout the past decade. RAM's have led the way in the explosive growth of metal oxide semiconductor (MOS) devices and technology. Two major reasons for the wide acceptance of MOS devices are first, MOS devices are providing increased bit densities; and second, the MOS devices are decreasing in cost per bit of memory.
The two types of semiconductor RAM memory are static RAM and dynamic RAM. Data stored in dynamic RAM is stored as a charge on a capacitor of a particular memory cell. During a read or write operation, the charge on the capacitor is determined by sense amplifiers and is transmitted to an output buffer. Sensing the stored charge on the capacitor destroys the contents of a particular memory cell. Therefore, automatic restoration or refreshing operations are required to preserve dynamic RAM.
Static RAM offers the advantages of nonvolatility for access and real time speed since no refreshing operation is required. Data in static RAM is stored in a latch and therefore, requires more transistors per bit than does dynamic RAM. Static RAM's are commonly used in high speed applications. Typically, the power dissipation of a static RAM can be an order of magnitude more then that of an equivalent size dynamic RAM. Further, unlike dynamic RAM, static RAM does not employ address multiplexing and thereby requires a greater number of input/output operations and a larger package then does dynamic RAM for an equivalent size memory.
Therefore, in digital systems where very fast memory access time is not required, dynamic RAM is widely used in the industry today.
With the advent of the widespread usage of microprocessors to perform such operations as switching control in smaller remotely located digital multiplexer systems, cost and size of circuitry becomes very important. Commonly used microprocessors are those such as the Intel 8085 and Intel 8086 models. Dynamic RAM in such microprocessor control systems must be refreshed at least every 2 milliseconds. The present invention is a dynamic memory refresh circuit implemented on a 1500 gate, 5 micron complementary MOS gate array. The gate array is packaged for small size in a 68 pin chip carrier. Only 600 of the 1500 gates in the gate array ship were required for the dynamic memory refresh circuit.